1. Field of the Invention
The present invention relates to a liquid crystal display device. More particularly, this invention relates to a liquid crystal display device having a wide display area, a highly fine definition and a high aperture ratio.
2. Description of the Related Arts
The construction of an active matrix substrate in a conventional liquid crystal display device is shown in FIG. 8.
In this liquid crystal display device, a plurality of pixel electrodes 12 are provided in a matrix on a transparent insulating substrate 11, and with each of these pixel electrodes 12 is connected a thin film transistor (hereinafter referred to as "TFT") 13 as a switching element. Moreover, a gate signal wiring 14 and a common additive capacitance wiring 15 as running in parallel therewith are formed alternately along each row of the pixel electrodes 12. A source signal wiring 16 is formed along each column of the pixel electrodes 12.
FIG. 9 is a plan view illustrating the construction of one pixel portion on an active matrix substrate in the conventional liquid crystal display device. Further, FIG. 10(a) is a sectional view of FIG. 9 viewed from the A-A' line, and FIG. 10(b) is a sectional view of FIG. 9 from the B-B' line (illustrating the TFT structure). As shown in FIG. 9, FIG. 10(a) and FIG. 10(b), a plurality of pixel electrodes 12 are provided in a matrix form, and the gate signal wiring 14 and the source signal wiring 16 are provided to perpendicularly cross each other, passing around the periphery of the pixel electrode 12. A part of these gate signal wiring 14 and source signal wiring 16 each overlaps the peripheral portion of the pixel electrode 12. Moreover, a TFT 13 as a switching element connected with the pixel electrode 12 is provided at the crossing portion of the gate signal wiring 14 and the source signal wiring 16. The gate signal wiring 14 is connected with the gate electrode of TFT 13 so that TFT 13 can be drived and controlled by a signal inputted into the gate electrode. Further, the source signal wiring 16 is connected with the source electrode of TFT 13, into which a data signal is inputted. Furthermore, the drain electrode of TFT 13 is connected with a connecting electrode 28 and also with the pixel electrode 12 via a contact hole 17, and then with the common additive capacitance wiring 15 via the connecting electrode 28.
Furthermore, as shown in FIG. 10(a), the gate signal wiring 14 and the common additive capacitance wiring 15 are formed on the transparent insulating substrate 11, and a gate insulating film 20 is formed so as to cover both wirings 14 and 15. The connecting electrode 28 connected with the drain electrode of the TFT 13 in FIG. 9 is also formed above the common additive capacitance wiring 15. In this way, an additive capacitance is generated by forming the common additive capacitance wiring 15 and the connecting electrode 28 with the gate insulating film 20 interposed in between. Furthermore, an interlayer insulating film 18 is formed on the substrate, and the pixel electrode 12 formed on the interlayer insulating film 18 is connected with the underlying connecting electrode 28 via the contact hole 17 formed to penetrate the interlayer insulating film 18 on the common additive capacitance wiring 15. This allows the pixel electrode 12 to be connected with the drain electrode of the TFT 13 of FIG. 9.
Furthermore, as shown in FIG. 10(b), a gate electrode 22, a gate insulating film 20, a silicon semiconductor layer 23 and an etching stopper 24 as a channel layer protective layer are formed sequentially on the transparent insulating substrate 11. Moreover, a first n.sup.+ silicon film 25 and a second n.sup.+ silicon film 26 are separately formed so that the first n.sup.+ silicon film 25 is electrically connected with a double-layer source electrode 27 and the second n.sup.+ silicon film 26 is electrically connected with a double-layer drain electrode 19.
The process for manufacturing the device as shown in FIG. 10(a) is now explained hereafter.
In FIG. 11(a), the TFT 13, the gate signal wiring 14, the common additive capacitance wiring 15, the source signal wiring 16 and the connecting electrode 28 are formed on the transparent insulating substrate 11, and the contact hole 17 is formed, as shown in FIG. 11(b), after the interlayer insulating film 18 is formed.
Subsequently, the pixel electrode 12 is formed on the interlayer insulating film 18, as shown in FIG. 11(c). The connection of the pixel electrode 12 with the drain electrode 19 is achieved by connecting (i) the connecting electrode 28 connected with the drain electrode 19 and (ii) the pixel electrode 12 in the contact hole 17.
The active matrix substrate is constructed as described above. Here, since the interlayer insulating film 18 is formed between the gate signal wiring 14, the common additive capacitance wiring 15 and the source signal wiring 16, and the pixel electrode 12, it becomes possible to allow the pixel electrode 12 to overlap each of these signal wirings. By introducing a liquid crystal display device of such a construction, it is possible to improve the opening ratio and also prevent ill orientation of liquid crystal by shielding the electric fields attributable to each signal wiring.
In the liquid crystal display device as described above, the pixel electrode 12 is allowed to overlap the source signal wiring 16, and so there is an increase in the capacitance between the source signal wiring 16 and the pixel electrode 12. Also, because the pixel electrode 12 is allowed to overlap the gate signal wiring 14 for driving the TFT 13 of the pixel, there is an increase in the capacitance between the gate signal wiring 14 and the pixel electrode 12 so that the field-through of writing voltage into the pixel attributable to the switching signal of TFT 13 and the like would become bigger as a defect.
In order to overcome these problems, the interlayer insulating film 18 having a film thickness in the order of .mu.m has heretofore been formed. As processes for forming such an interlayer insulating film 18, for example, there has been used a process for applying a photosensitive organic resin according to a spin coat method and then patterning by exposing and developing with an alkali.
In the case where a thick interlayer insulating film 18 was formed according to the conventional process, it is necessary to provide a taper in the contact hole 17 for ensuring the connection between the pixel electrode 12 and the underlying connecting electrode 28 and in particular for improving the coverage of the pixel electrode 12. Assuming here that the contact hole 17 had a bottom diameter of 5 .mu.m, the aperture surface of the contact hole 17 would have a width of not less than 10 .mu.m, taking into consideration a tapered region of the contact hole 17, alignment accuracy and the like. If the contact hole 17 had a tapered region larger than the metal layer of the underlying common additive capacitance wiring 15, leakage of light would occur to lower the quality of contrast. Therefore, it has been necessary to have the width of such an underlying common additive capacitance wiring larger than the contact region.
However, if the width of the common additive capacitance wiring was made larger than 10 .mu.m in accordance with the above-mentioned example, it would cause an inconvenience of lowered opening ratio. Particularly, since the size of a pixel tends to decrease in accordance with the recent spread of highly fine definition of liquid crystal display devices, enlargement of the width of the common additive capacitance wiring 15 would result in remarkably impairing the performance of the liquid crystal display devices. Thus, an attempt was made to reduce the width of the aperture surface of the contact hole 17 by enlarging a tapering angle for the purpose of preventing leakage of light without widening the width of the common additive capacitance wiring 15. However, the enlargement of the tapering angle caused breaking of wiring because of deteriorated coverage of the pixel electrode 12 formed by the sputtering method, which resulted in causing a number of ill connections of the pixel electrode 12 with the underlying connecting electrode 28.